void Driver_Initial(void) { Driver_Reset(); //************* Start Initial Sequence **********// Write_REG_Index(0xE5); Write_REG_Data(0x78F0); Write_REG_Index(0x01); //Driver output control Write_REG_Data(0x0100); //SM, SS Write_REG_Index(0x02); //LCD driving wave control Write_REG_Data(0x0000); //Frame field inversion Write_REG_Index(0x03); //Entry mode Write_REG_Data(0x1030); Write_REG_Index(0x08); //display control 2 Write_REG_Data(0x0202); Write_REG_Index(0x09); //display control 3 Write_REG_Data(0x0000); Write_REG_Index(0x0A); //dispay control 4 Write_REG_Data(0x0000); Write_REG_Index(0x0C); //RGB dispay interface control 1 Write_REG_Data(0x0001); Write_REG_Index(0x0D); //frame marker position Write_REG_Data(0x0000); //************* Power On Sequence **********// Write_REG_Index(0x10); Write_REG_Data(0x0000); Write_REG_Index(0x11); Write_REG_Data(0x0007); Write_REG_Index(0x12); Write_REG_Data(0x0000); Write_REG_Index(0x13); Write_REG_Data(0x0000); Write_REG_Index(0x07); //display control 1 Write_REG_Data(0x0001); Delay(600); Write_REG_Index(0x10); //VGH VGL Write_REG_Data(0x1190); Write_REG_Index(0x11); //VCI1 Write_REG_Data(0x0227); Delay(600); Write_REG_Index(0x12); Write_REG_Data(0x0096); Delay(600); Write_REG_Index(0x13); //VCOM Write_REG_Data(0x1A00); Write_REG_Index(0x29); Write_REG_Data(0x0021); Write_REG_Index(0x2B); Write_REG_Data(0x000C); Delay(600); Write_REG_Index(0x20); //GRAM Horizontal/Vertical Address Set Write_REG_Data(0x0000); Write_REG_Index(0x21); Write_REG_Data(0x0000); //************* Set GRAM area **********// Write_REG_Index(0x50); Write_REG_Data(0x0000); Write_REG_Index(0x51); Write_REG_Data(0x00EF); Write_REG_Index(0x52); Write_REG_Data(0x0000); Write_REG_Index(0x53); Write_REG_Data(0x013f); Write_REG_Index(0x60); Write_REG_Data(0xa700); Write_REG_Index(0x61); Write_REG_Data(0x0000); //REV Write_REG_Index(0x6A); Write_REG_Data(0x0000); //************* Partial Display Control **********// Write_REG_Index(0x80); //partial image 1 display position Write_REG_Data(0x0000); Write_REG_Index(0x81); //partial image 1 RAM start/end address Write_REG_Data(0x0000); Write_REG_Index(0x82); Write_REG_Data(0x0000); Write_REG_Index(0x83); Write_REG_Data(0x0000); Write_REG_Index(0x84); Write_REG_Data(0x0000); Write_REG_Index(0x85); Write_REG_Data(0x0000); //************* Partial Display Control **********// Write_REG_Index(0x07); Write_REG_Data(0x0133); }